Design of approximate-TMR using approximate library and heuristic approaches
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http://hdl.handle.net/10045/82609
Títol: | Design of approximate-TMR using approximate library and heuristic approaches |
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Autors: | Albandes, Iuri | Serrano-Cases, Alejandro | Martins, M. | Martínez-Álvarez, Antonio | Cuenca-Asensi, Sergio | Kastensmidt, Fernanda L. |
Grups d'investigació o GITE: | UniCAD: Grupo de investigación en CAD/CAM/CAE de la Universidad de Alicante |
Centre, Departament o Servei: | Universidad de Alicante. Departamento de Tecnología Informática y Computación |
Paraules clau: | ATMR | Approximate circuits | Fault tolerance | Genetic algorithm |
Àrees de coneixement: | Arquitectura y Tecnología de Computadores |
Data de publicació: | de setembre-2018 |
Editor: | Elsevier |
Citació bibliogràfica: | Microelectronics Reliability. 2018, 88-90: 898-902. doi:10.1016/j.microrel.2018.07.115 |
Resum: | Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate versions of the target circuit, has emerged in recent years as an alternative to partial hardware replication where designers can explore reduced area overhead combined with some compromise on fault masking. This work presents a novel approach for implementing approximate TMR that combines the approximate gate library (ApxLib) technique with heuristics. The algorithm initially defines the gates to be approximated using testability and observability measures and then choose the gate transformation based on the bits difference. Experimental results compare the proposed new approach with another state of the art technique that uses approximate gate libraries with genetic algorithm showing a good trade-off between the ATMR schemes efficiency in terms of area and fault masking and the computational effort needed to generate them. |
Patrocinadors: | This research was supported by Federal University of Rio Grande Do Sul (UFRGS) and was also funded by the Spanish Ministry of Economy and Competitiveness and the European Regional Development Fund with the project Evaluacion temprana de los efectos de radiacion mediante simulacion y virtualizacion. Estrategias de mitigacion en arquitecturas de microprocesadores avanzados (Ref: ESP2015-68245-C4-3-P MINECO/FEDER, UE). |
URI: | http://hdl.handle.net/10045/82609 |
ISSN: | 0026-2714 (Print) | 1872-941X (Online) |
DOI: | 10.1016/j.microrel.2018.07.115 |
Idioma: | eng |
Tipus: | info:eu-repo/semantics/article |
Drets: | © 2018 Published by Elsevier Ltd. |
Revisió científica: | si |
Versió de l'editor: | https://doi.org/10.1016/j.microrel.2018.07.115 |
Apareix a la col·lecció: | INV - UNICAD - Artículos de Revistas |
Arxius per aquest ítem:
Arxiu | Descripció | Tamany | Format | |
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2018_Albandes_etal_MicroelectrReliab_final.pdf | Versión final (acceso restringido) | 766,76 kB | Adobe PDF | Obrir Sol·licitar una còpia |
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