Sanchez-Romero, Jose-Luis, Mora, Higinio, Mora Pascual, Jerónimo Manuel, Jimeno-Morenilla, Antonio
Architecture implementation of an improved decimal CORDIC method
SÁNCHEZ ROMERO, José Luis, et al. "Architecture implementation of an improved decimal CORDIC method". En: IEEE International Conference on Computer Design, 2008: ICCD 2008. Piscataway, NJ : IEEE, 2008. ISBN 978-1-4244-2657-7, pp. 95-100
URI: http://hdl.handle.net/10045/11823
DOI: 10.1109/ICCD.2008.4751846
ISSN: 1063-6404
ISBN: 978-1-4244-2657-7
Abstract: 
Since radix-10 arithmetic has been gaining renewed importance over the last few years, high performance decimal systems and techniques are highly demanded. In this paper, a modification of the CORDIC method for decimal arithmetic is proposed so as to improve calculations. The algorithm works with BCD operands and no conversion to binary is needed. A significant reduction in the number of iterations in comparison to the original decimal CORDIC method is achieved. The experiments showing the advantages of the new method are described. Also, the results with regard to delay obtained by means of an FPGA implementation of the method are shown.
Keywords:CORDIC, Decimal arithmetic
IEEE
info:eu-repo/semantics/bookPart