Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques

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Títol: Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques
Autors: Chielle, Eduardo | Rosa, Felipe | Rodrigues, Gennaro S. | Tambara, Lucas A. | Tonfat, Jorge | Macchione, Eduardo | Aguirre, Fernando | Added, Nemitala | Medina, Nilberto | Aguiar, Vitor | Silveira, Marcilei A.G. | Ost, Luciano | Reis, Ricardo | Cuenca-Asensi, Sergio | Kastensmidt, Fernanda L.
Grups d'investigació o GITE: UniCAD: Grupo de investigación en CAD/CAM/CAE de la Universidad de Alicante
Centre, Departament o Servei: Universidad de Alicante. Departamento de Tecnología Informática y Computación
Paraules clau: Aerospace applications | Error detection | Fault coverage | Fault tolerance | Mitigation techniques | Processors | Reliability | Soft errors | Software techniques
Àrees de coneixement: Arquitectura y Tecnología de Computadores
Data de publicació: d’agost-2016
Editor: IEEE
Citació bibliogràfica: IEEE Transactions on Nuclear Science. 2016, 63(4): 2208-2216. doi:10.1109/TNS.2016.2525735
Resum: ARM processors are leaders in embedded systems, delivering high-performance computing, power efficiency, and reduced cost. For this reason, there is a relevant interest for its use in the aerospace industry. However, the use of sub-micron technologies has increased the sensitivity to radiation-induced transient faults. Thus, the mitigation of soft errors has become a major concern. Software-Implemented Hardware Fault Tolerance (SIHFT) techniques are a low-cost way to protect processors against soft errors. On the other hand, they cause high overheads in the execution time and memory, which consequently increase the energy consumption. In this work, we implement a set of software techniques based on different redundancy and checking rules. Furthermore, a low-overhead technique to protect the program execution flow is included. Tests are performed using the ARM Cortex-A9 processor. Simulated fault injection campaigns and radiation test with heavy ions have been performed. Results evaluate the trade-offs among fault detection, execution time, and memory footprint. They show significant improvements of the overheads when compared to previously reported techniques.
Patrocinadors: This work was supported in part by CNPq and CAPES, Brazilian agencies.
URI: http://hdl.handle.net/10045/62196
ISSN: 0018-9499 (Print) | 1558-1578 (Online)
DOI: 10.1109/TNS.2016.2525735
Idioma: eng
Tipus: info:eu-repo/semantics/article
Drets: © 2016 IEEE
Revisió científica: si
Versió de l'editor: http://dx.doi.org/10.1109/TNS.2016.2525735
Apareix a la col·lecció: INV - UNICAD - Artículos de Revistas

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