Selective SWIFT-R. A Flexible Software-Based Technique for Soft Error Mitigation in Low-Cost Embedded Systems

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Título: Selective SWIFT-R. A Flexible Software-Based Technique for Soft Error Mitigation in Low-Cost Embedded Systems
Autor/es: Restrepo Calle, Felipe | Martínez-Álvarez, Antonio | Cuenca-Asensi, Sergio | Jimeno-Morenilla, Antonio
Grupo/s de investigación o GITE: UniCAD: Grupo de investigación en CAD/CAM/CAE de la Universidad de Alicante
Centro, Departamento o Servicio: Universidad de Alicante. Departamento de Tecnología Informática y Computación
Palabras clave: Fault tolerance | Reliability | Embedded systems | Soft errors | Single Event Upset (SEU) | COTS electronic components
Área/s de conocimiento: Arquitectura y Tecnología de Computadores
Fecha de publicación: dic-2013
Editor: Springer Science+Business Media New York
Cita bibliográfica: Journal of Electronic Testing. 2013, 29(6): 825-838. doi:10.1007/s10836-013-5416-6
Resumen: Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their programmability and cost-effectiveness. Recent advances in electronic technologies have allowed remarkable improvements in their performance. However, they have also made microprocessors more susceptible to transient faults induced by radiation. These non-destructive events (soft errors), may cause a microprocessor to produce a wrong computation result or lose control of a system with catastrophic consequences. Therefore, soft error mitigation has become a compulsory requirement for an increasing number of applications, which operate from the space to the ground level. In this context, this paper uses the concept of selective hardening, which is aimed to design reduced-overhead and flexible mitigation techniques. Following this concept, a novel flexible version of the software-based fault recovery technique known as SWIFT-R is proposed. Our approach makes possible to select different registers subsets from the microprocessor register file to be protected on software. Thus, design space is enriched with a wide spectrum of new partially protected versions, which offer more flexibility to designers. This permits to find the best trade-offs between performance, code size, and fault coverage. Three case studies have been developed to show the applicability and flexibility of the proposal.
Patrocinador/es: This work was funded by the Ministry of Science and Innovation in Spain with the project ‘RENASER+: Integral Analysis of Digital Circuits and Systems for Aerospace Applications’ (TEC2010-22095-C03-01).
URI: http://hdl.handle.net/10045/40363
ISSN: 0923-8174 (Print) | 1573-0727 (Online)
DOI: 10.1007/s10836-013-5416-6
Idioma: eng
Tipo: info:eu-repo/semantics/article
Derechos: The final publication is available at Springer via http://dx.doi.org/10.1007/s10836-013-5416-6
Revisión científica: si
Versión del editor: http://dx.doi.org/10.1007/s10836-013-5416-6
Aparece en las colecciones:INV - UNICAD - Artículos de Revistas

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